The development of new portable electronic products, such as the laptop computer, is currently of great worldwide interest. Miniaturization of the various component systems (memories, displays, and so forth) for such products requires that the necessary circuits be packed in as small a volume as possible. Packing circuits into a small volume also reduces parasitic capacitance and improves signal propagation time between circuits. One approach to this requirement is to increase the scale of integration in order to obtain all of the required functions from a circuit made from a single wafer. Unfortunately, efforts to create full-wafer circuitry have encountered unacceptable yield losses owing to the large circuit size. In the specific area of active matrix displays, a similar problem results in attempting the scale-up of the display size to and beyond the 256K pixel level.
Active matrix (AM) displays generally consist of flat-panels consisting of liquid crystals or electroluminescent materials which are switched xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d by electric fields emanating from pixel electrodes charged by thin-film transistors (TFT""s) co-located with each liquid crystal or electroluminescent pixel area. These AM displays are expected to supplant cathode ray tube (CRT) technology and provide a more highly defined television picture or data display. The primary advantage of the active matrix approach, using TFT""s, is the elimination of cross-talk between pixels, and the excellent grey scale that can be attained with TFT-compatible liquid crystal displays (LCD""s).
Flat panel displays employing LCD""s generally include five different layers: a white light source layer, a first polarizing filter layer that is mounted on one side of a circuit panel on which the TFT""s are arrayed to form pixels, a filter plate layer containing at least three primary colors arranged into pixels, and finally a second polarizing filter layer. A volume between the circuit panel and the filter plate is filled with a liquid crystal material. This material rotates the polarization of light passing through it when an appropriate electric field is applied across it. Thus, when a particular pixel electrode of the display is charged up by an associated TFT, the liquid crystal material rotates polarized light being transmitted through the material so that it will pass through the second polarizing filter and be seen by the viewer.
The primary approach to TFT formation over the large areas required for flat panel displays has involved the use of films of amorphous silicon which has previously been developed for large-area photovoltaic devices. Although the TFT approach has proven to be feasible, the use of amorphous silicon compromises certain aspects of the panel performance. For example, amorphous silicon TFT""s lack the frequency response needed for large area displays due to the low electron mobility inherent in amorphous material. Thus, the use of amorphous silicon limits display speed, and is also unsuitable for the fast logic needed to drive the display.
Owing to the limitations of amorphous silicon, other alternative materials are being considered, such as, polycrystalline silicon, or laser recrystallized silicon. Thin films, less than about 0.4 microns, of these materials are usually formed on glass which generally restricts further circuit processing to low temperatures.
The formation of large active-matrix displays is hampered by the unavailability of large-area single crystal Si material. Thus the conventional approach is to use thin-film amorphous (xcex1-Si) or polycrystalline Si (poly-Si) wafers. The required number of thin-film transistors (TFT""s), combined with the large number of driver circuits and the thin-film material defects inherent in xcex1-Si or poly-Si, leads to unacceptable yield and quality problems when the entire display is to be fabricated as a unit.
A need exists, therefore, for a relatively inexpensive way to reliably form hybrid high density electronic circuits, including active matrices, memories, and other devices, in a modular approach that permits small high-quality parts or circuits to be assembled into complete large-area high-quality complex devices.
The present invention comprises a method, and resulting apparatus, for fabricating complex hybrid multi-function circuitry a common module body, such as a substrate or superstrate, by using silicon thin film transfer processes to remove areas or tiles of circuits, formed in Si thin-films, and transferring, locating and adhering the removed tiles to a common module body. The removal of areas or tiles is hereinafter referred to, generally, as xe2x80x9cdicing.xe2x80x9d The process of transferring, locating and adhering is generally referred to as xe2x80x9ctiling.xe2x80x9d
The films may be formed of xcex1-Si, poly-Si, or x-Si depending upon the desired circuit parameters. Elements of one circuit are then interconnected to elements of another circuit by conventional photolithographically patterned thin film metallization techniques. Direct laser writing or erasing may be used for repair or modification of interconnects.
The transfer may be accomplished in either of two waysxe2x80x94single transfer or double transfer. In the single transfer process, the desired Si circuitry is formed on a thin film Si substrate; the Si circuits are diced, i.e., divided into dice or tiles containing one or more circuits; the dice or tiles are then tiled, i.e., sequentially registered onto a common module body and sequentially adhered to the module body. After all the dice or tiles are adhered, all the Si substrates are removed in one process and the circuits interconnected. Alternately, the Si substrates may be sequentially removed if more precise alignment is required.
In the double transfer process, the circuits are transferred to an intermediary transfer or carrier body and then the substrates are removed. Dicing may occur before or after the first transferral. The thin film circuitry is supported by the transfer body until transfer to the common module body is appropriate. The circuitry is then tiled, i.e., sequentially transferred, registered and adhered to the common module body. If the transfer body is sufficiently thin, the transfer body may be left on the circuitry. If not, it is removed and circuit interconnections made, as required.
In a preferred embodiment, the common module forms an active matrix (AM) LCD panel fabricated in accordance with the invention. The circuit panel for the AMLCD is formed by transferring to a common module substrate or superstrate, multiple x-Si and/or xcex1-Si or poly-Si thin film tiles upon which circuits may have been formed, and wherein each tile is obtained as a unit from one or more wafers. During transfer, the tiles are registered with respect to one another. Circuits are then interconnected as necessary. Registration is accomplished by well-known X-Y micropositioning equipment. Adherence and planarity are achieved using optically transparent adhesives which fill in voids left in forming circuitry. Trimming of substrate edges may be required to obtain precise circuit dimensions needed for proper alignment on the module body.
Other preferred embodiments of the present invention relate to the formation of three-dimensional circuits and devices. Significantly, these three dimensional circuits and devices provide for high density circuitry in small areas. As such, three-dimensional (3-D) circuits and devices can be used to fabricate high density electronic circuitry including stacked memories, multi-functional parallel processing circuits, high density low-power CMOS static RAMs, peripheral drive circuitry for display panels and a plurality of high-speed low-power CMOS devices.
In accordance with the present invention, a preferred fabrication process comprises single and double transfer of silicon films and backside processing of said films for providing various 3-D circuits and devices. In one preferred embodiment, a 3-D double gate MOSFET device can be fabricated. First, a standard MOSFET having drain, source and gate regions is formed in a silicon layer of an SOI structure by any suitable technique. Next, the MOSFET is single transferred to a superstrate for backside processing. A region of the insulating layer is removed to expose a backside region of the silicon layer. A second gate is then formed adjacent the backside region of the silicon layer opposite the first gate. A conductive contact is attached to the second gate, thereby providing a 3-D double gate MOSFET.
In another embodiment of the present invention, a 3-D double gate MOSFET inverter is fabricated such that its n-channel MOSFET and its p-channel MOSFET share the same body with their respective channels disposed on opposite sides of the shared body. In fabricating this inverter, a silicon layer is formed over an insulating layer on a substrate. After the silicon is patterned into an island, a series of doping steps are performed on the silicon to produce a first MOSFET having a first drain, a first source and channel region (which is a portion of the shared body region). The first drain, first source and channel regions are disposed along a first axis in a plane extending through the silicon. Another series of doping steps are subsequently performed on the silicon to produce a second MOSFET having a second drain, a second source and a channel region which are disposed along a second axis extending perpendicular to the first axis. A first gate is then formed on one side of the plane of the silicon, and contacts are attached to the first source, first drain, first gate, second source and second drain. The silicon is bonded to a superstrate and the substrate is removed for backside processing. Accordingly, a region of the insulating layer is removed to exposed a backside region of the silicon island and a second gate is formed. The second gate is positioned on the opposite side of the plane of the silicon island as the first gate over the channel region. A contact is then attached to the second gate and the two gates can then be electrically connected.
In another embodiment, another 3-D double gate MOSFET inverter is formed of a pair of vertically stacked MOSFETs. The fabrication sequence involves forming a first MOSFET device in a first silicon layer over a first substrate, and a second MOSFET device in a second silicon layer over a second substrate. The first MOSFET device is transferred to a superstrate, and the second MOSFET device is transferred to a optically transmissive substrate. Next, the first silicon layer is stacked onto the second silicon layer such that the two MOSFET devices are vertically aligned. The MOSFETs are then electrically interconnected to provide an 3-D inverter circuit.
In yet another embodiment, a vertical bipolar transistor is fabricated in accordance with the principles of the invention. The fabrication process begins with providing a silicon layer over an insulating layer on a substrate. Next, a series of doping steps are performed to produce a collector region, an emitter region and a base region. Conductive contacts are then formed for the collector, emitter and base. The structure can be single transferred to a superstrate for backside processing. To that end, a region of the insulating layer is removed to expose a backside region of the silicon layer. A metal layer is applied over the exposed backside of the silicon and sintered.